Peter Lawton G7IXH



E-Mail enquiries

Home   



      Huff & Puff overview



The first design for the Huff & Puff stabiliser was published in 1973 by the late Klaas Spaargaren, PA0KSB. It was thoroughly ground-breaking and a work of originality and genius. However, in the early stages of an enterprise we can only "see as through a glass, darkly", and all but the most docile of VFOs were beyond the stabilising powers of this first H&P.

So after a long wait, in 1996 Klaas published his VFO derived clock ('type 2') version. The type 2 has a considerably stronger lock at VFO frequencies below about 40MHz, though it suffers from the disadvantage that the step height is not independent of VFO frequency. This was the first practical Huff and Puff design.

The third advance was in 1998 when QEX magazine published my 'Fast Huff & Puff' stabiliser design (thanks to Klaas who tested and endorsed it and to Pat Hawker, who first published the circuit and an outline of its operation in 'Technical Topics', for their encouragement).

The earlier H&Ps had an unecessary weakness. A count will take 1/10 second (for a 10Hz step), and early H&P's waited until one count was finished, and its "correction" applied to the VFO, before starting the next count. So corrections would be applied every 1/10th second. But a tenth of a second between "corrections" is a very long time if you are hoping to keep a VFO within a ten Hz band, especially when just switched on). The 'fast' epithet derives from the most significant difference from these previous versions which is that in the fast stabiliser there are many counts going on at the same time, all at different stages of completion, and so the rate at which new corrections are applied to the VFO can be hundreds of times greater. This allows a much quicker response to any VFO frequency fluctuations and hence confers the ability to counteract a far greater drift rate. This design can stop just about any drifting VFO dead in its tracks.

A brief explanation of how the "fast" H&P works is as follows...

The device has three main parts: -

1) The digital frequency changer. This is simply a clocked data latch with the signal to be stabilised (or more likely, a divided-down version of it) applied to its input. The output of such a device is interesting. If you gradually increase the input frequency, the frequency of the output (which is always a square wave) goes repetitively and evenly up and down between zero Hz and a maximum of half the clock frequency (which as has been said earlier would typically be of the order of 500Hz or more).

2) A frequency to voltage convertor applied to the output from the data latch. This is done by splitting the output from the data latch into two streams, one stream going directly to one input of an XOR gate, the other being delayed by one (or more, preferably many more) clock cycles before going to the other input of the XOR.

The XOR output will be a stream of pulses (not in general a square wave), but the interesting (and useful) thing about it is that the average voltage of the output is a function of its input frequency. You can test this with an old-fashioned voltmeter at the XOR output which will repetitively cycle between 0 and 5 volts and back to 0 volts as you gradually and evenly increase the frequency of the input to the data latch. It would have to be an old fashioned voltmeter with a heavy coil and pointer in order to show the AVERAGE voltage - remember that the output from the XOR consists of a stream of pulses, so at any particular instant it will either be high (5V) or it will be low (0V).

3) Lastly, an integrator with a standing bias of 2.5 volts. The output of the integrator controls a varicap placed across the VFO coil.

The effect of all of the above is that the vfo is constrained to head for the frequency which produces an average XOR output of 2.5 volts. It is important to realise (I'll say it again!) that the XOR output at an instant can only be either 0 volts or 5 volts. An average of 2.5 volts means that it is a square wave at that point (half the time "high", half the time "low"). Note finally that the "step" (distance between lock points, in Hz) is a function (among other things) of the delay time between the two data streams in the frequency to voltage convertor. It is best to achieve the required delay for your chosen "step" by using a fast clock with many delay stages (use a shift register, say) rather than a single delay stage and a slower clock. The faster the clock, the more powerful is the stabiliser, simply because it will catch any drift sooner and correct it before it can accumulate.

And a final, final note - The above describes a "type 1" stabiliser (uses the reference frequency derived from a crystal oscillator for the two "clock" inputs to the stabiliser. The "clock" and the "signal" can be swapped over to produce a "type 2" stabiliser, which will have somewhat different characteristics (in particular a dependence of the "step" on the signal frequency).

A few numbers: -
For a type 1 stabiliser I divide the signal frequency by two, simply to ensure it is perfectly square (the stabiliser still works if the input has an asymmetrical mark-space ratio, but will have a bias towards moving the vfo in a particular direction and this will manifest itself when the vfo is tuned and will result in the stabiliser eventually saturating). So, if the vfo frequency is (say) 14MHz, we are feeding 7MHz into the stabiliser at the signal input connection.
Clock frequency - Because of this frequency division of the vfo before it is applied to the stabiliser, if we want a 10Hz step for the vfo the stabiliser itself must have a 5HZ step. This means we need a delay within the frequency/voltage convertor of 1/5 second. If we have (say) a 100 stage shift register, each stage must therefore produce a delay of 1/500 second, so we need a 500Hz clock.
This can be obtained by dividing down from a crystal oscillator.

The formula for the VFO step for a type 1 stabiliser is
Step (in Hz) = ((2^n) x fC)/N where n = no of stages of division between the VFO and the stabiliser, fC is the clock frequency applied to the stabiliser (in Hz), and N is the number of shift register stages within the stabiliser.

If the signal is used for the clock, the formula for the VFO step is
Step (in Hz) = (fV^2)/(N x 2^n x fC) where fV is the vfo frequency, n = no of stages of division between the VFO and the stabiliser, fC is the clock frequency applied to the stabiliser (in Hz), and N is the number of shift register stages within the stabiliser. So for example, to get a step of 8Hz with a vfo at 14MHz and a 100 stage shift register, you could have 13 stages of VFO division before the stabiliser, and a reference frequency of 30MHz derived from a crystal oscillator (use a 60MHz oscillator unit and divide by 2 to square it up).

RIT
In my experience the fast H&P has no problem with RIT, returning to precisely the correct frequencies when the VFO is switched between transmit and receive and vice versa.

Applications for the H&P:

The fast H&P has a powerful lock if the parameters are adjusted correctly - BUT it is wise to realise that if the lock of a H&P is broken, there is no mechanism for it to return to its previous frequency. Because of this, it is absolutely necessary to isolate it and its associated VFO from mechanical and electrical transients.This may be more difficult to accomplish in valve (tube) radios. In such circumstances one might be better off using Ron Taylor's X-Lock which I believe retains a memory of the frequency, and will try to return to it, as long as it hasn't been thrown too far away from it by the transient.
The H&P will perform best with purpose-built, solid state equipment, where its performance can be quite spectacular. Another point, which applies to all stabilisation methods AFIK is that with a wide-range VFO you have to make a compromise on the integrator/varicap parameters. It's best to optimise at the HF end.

DOWNLOADS
If any of these downloads don't install or don't work then please let me know. Hit "E-Mail enquiries' above and send me a mail.
Any other comments welcome.

1) Fast Huff & Puff simulator program
Download Fast Huff & Puff simulator program (1.7Mb)

Set your own parameters and watch a simulation of the fast Huff & Puff in action

The program is a tidied-up version of the software used to develop the fast H&P.
Besides being interesting to watch, the program will tell you the maximum drift a stabiliser with given parameters can handle so you can optimise the stabiliser parameters.


2) Visual Aid 1
Download Fast Huff & Puff visual aid 1 (1.8Mb)


Shows waveforms at outputs of D-Type latch, shift register and XOR gate for variable VFO frequency and number of shift register stages.