Peter Lawton G7IXH



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      Huff & Puff overview



The first design for the Huff & Puff stabiliser was published in 1973 by the late Klaas Spaargaren, PA0KSB. However, all but the most stable of VFOs were beyond the stabilising powers of this first H&P and it was only in 1996 that Klaas described the first practical Huff and Puff circuit.

The third step was in 1998 when QEX magazine published my article, giving details of a new design which I called the 'Fast' Huff & Puff stabiliser (thanks to Klaas who tested and endorsed it and to Pat Hawker, who first published the circuit and an outline of its operation in 'Technical Topics', for their encouragement).

The fast H&P addresses two weaknesses in earlier designs, i.e. (firstly) slow response to VFO frequency changes, and (secondly) unnecessary over-complication. It has a much quicker response to any VFO frequency fluctuations and hence confers the ability to counteract a far greater drift rate, and has fewer components. If you are building a stabiliser, the Fast H&P is the only circuit to use. Previous designs are of interest only.

A brief description of the fast H&P is as follows...

The heart of the device consists of only two ICs: -

1) A (High Frequency first stage) shift register. The VFO is applied to the input. I tend to use a separate D-type latch for the first stage. This allows the use of a many stage (but low frequency capable) shift register IC for the rest of the stages. The more stages the better. In the diagram beneath the "IN" point is from the output of the D type latch (or from the output of the first stage of the shift register).

2) An XOR gate. The two inputs to which are a) from the first stage output of the shift register, and b) from the last stage output of the shift register.

The XOR output will be a stream of pulses (not in general a square wave), but the interesting (and useful) thing about it is that the average voltage of the output is a function of its input frequency. You can test this with an old-fashioned voltmeter at the XOR output which will repetitively cycle between 0 and 5 volts and back to 0 volts as you gradually and evenly increase the frequency of the input to the data latch. It would have to be an old fashioned voltmeter with a heavy coil and pointer in order to show the AVERAGE voltage - remember that the output from the XOR consists of a stream of pulses, so at any particular instant it will either be high (5V) or it will be low (0V).

3) Lastly, an integrator with a standing bias of 2.5 volts. The output of the integrator controls a varicap placed across the VFO coil.

The effect of all of the above is that the vfo hovers around the frequency which produces an average XOR output of 2.5 volts. It is important to realise (I'll say it again!) that the XOR output at an instant can only be either 0 volts or 5 volts. An average of 2.5 volts means that it is a square wave at that point (half the time "high", half the time "low"). Note finally that the "step" (distance between lock points or "hover points", in Hz) is a function (among other things) of the delay time between the two data streams in the frequency to voltage convertor. It is best to achieve the required delay for your chosen "step" by using a fast clock with many delay stages (use a shift register, say) rather than a single delay stage and a slower clock. The faster the clock, the more powerful is the stabiliser, simply because it will catch any drift sooner and correct it before it can accumulate.

And a final, final note - The above describes a "type 1" stabiliser (uses the reference frequency derived from a crystal oscillator for the two "clock" inputs to the stabiliser. The "clock" and the "signal" can be swapped over to produce a "type 2" stabiliser, which will have somewhat different characteristics (in particular a dependence of the "step" on the signal frequency).

A few numbers: -
For a type 1 stabiliser I divide the signal frequency by two, simply to ensure it is perfectly square (the stabiliser still works if the input has an asymmetrical mark-space ratio, but will have a bias towards moving the vfo in a particular direction and this will manifest itself when the vfo is tuned and will result in the stabiliser eventually saturating). So, if the vfo frequency is (say) 14MHz, we are feeding 7MHz into the stabiliser at the signal input connection.
Clock frequency - Because of this frequency division of the vfo before it is applied to the stabiliser, if we want a 10Hz step for the vfo the stabiliser itself must have a 5HZ step. This means we need a delay within the frequency/voltage convertor of 1/5 second. If we have (say) a 100 stage shift register, each stage must therefore produce a delay of 1/500 second, so we need a 500Hz clock.
This can be obtained by dividing down from a crystal oscillator.

The formula for the VFO step for a type 1 stabiliser is
Step (in Hz) = ((2^n) x fC)/N where n = no of stages of division between the VFO and the stabiliser, fC is the clock frequency applied to the stabiliser (in Hz), and N is the number of shift register stages within the stabiliser.

If the signal is used for the clock, the formula for the VFO step is
Step (in Hz) = (fV^2)/(N x 2^n x fC) where fV is the vfo frequency, n = no of stages of division between the VFO and the stabiliser, fC is the clock frequency applied to the stabiliser (in Hz), and N is the number of shift register stages within the stabiliser. So for example, to get a step of 8Hz with a vfo at 14MHz and a 100 stage shift register, you could have 13 stages of VFO division before the stabiliser, and a reference frequency of 30MHz derived from a crystal oscillator (use a 60MHz oscillator unit and divide by 2 to square it up).

RIT
In my experience the fast H&P has no problem with RIT, returning to precisely the correct frequencies when the VFO is switched between transmit and receive and vice versa.

Applications for the H&P:

The fast H&P has a powerful lock if the parameters are adjusted correctly - BUT it is wise to realise that if the lock of a H&P is broken, there is no mechanism for it to return to its previous frequency. Because of this, it is absolutely necessary to isolate it and its associated VFO from mechanical and electrical transients.This may be more difficult to accomplish in valve (tube) radios. In such circumstances one might be better off using Ron Taylor's X-Lock which I believe retains a memory of the frequency, and will try to return to it, as long as it hasn't been thrown too far away from it by the transient.
The H&P will perform best with purpose-built, solid state equipment, where its performance can be quite spectacular. Another point, which applies to all stabilisation methods AFIK is that with a wide-range VFO you have to make a compromise on the integrator/varicap parameters. It's best to optimise at the HF end.

DOWNLOADS
If any of these downloads don't install or don't work then please let me know. Hit "E-Mail enquiries' above and send me a mail.
Any other comments welcome.

1) Fast Huff & Puff simulator program
Download Fast Huff & Puff simulator program (1.7Mb)

Set your own parameters and watch a simulation of the fast Huff & Puff in action

The program is a tidied-up version of the software used to develop the fast H&P.
Besides being interesting to watch, the program will tell you the maximum drift a stabiliser with given parameters can handle so you can optimise the stabiliser parameters.


2) Visual Aid 1
Download Fast Huff & Puff visual aid 1 (1.8Mb)


Shows waveforms at outputs of D-Type latch, shift register and XOR gate for variable VFO frequency and number of shift register stages.